An “assertion” in a hardware description language (HDL), such as SystemVerilog, is a statement that determines whether or not the state of the simulated circuit design satisfies certain specified conditions. Assertions can be used to test and debug circuit designs. Assertions can test the state of the simulation at a particular moment of the simulation or over a period of time during the simulation.
In SystemVerilog, for example, a “sequence” can be used to test an assertion over a period of time. An assertion having a sequence tests for the occurrence of a series of events over a period of time during the simulation.
Efficient use of computer resources is important during simulation. Costly computer requirements and long runtimes add to production costs and can delay product releases. Thus, a modeling system that reduces memory and computational requirements is desirable.